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ST70137
UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER
ST70137 HARDWARE FEATURES DESCRIPTION ST70137 is STMicroelectronics UNICORNTM chipset ADSL DMT transceiver for controllerless ADSL CPE modem. UNICORNTM allows to develop easily and quickly low cost ADSL CPE modem for PC environment. UNICORNTM is made of two devices, ST70137 and ST70136 or ST70134 (CPE ADSL Analog Front End). ST70137 provides PCI and USB interface. PCI is used to build ADSL CPE modem bundled in the PC, USB interface is used to build external bus powered ADSL modem. ST70137 is compliant with ITU 992.1 Annexe A and B, with ITU 992.2 and with ANSI T1.413. UNICORNTM chipset is delivered with a complete PC software suite for Microsoft Windows 98, Windows 2000 and Windows NT. NDIS5.0 PCI driver and USB driver with ADSL modem control and ATM device driver are provided assuring full ATM support. Configuration and diagnostic tools are also provided. UNICORNTM chipset and PC software ensure interoperability with the most deployed DSLAM.
s SUPPORT DIGITAL SIGNAL PROCESSING
REQUIREMENTS FOR ONE ADSL CPE CHANEL (ITU-R)
s COMPLIANT WITH ITU 992.1 (ADSL FULL
RATE) ANNEXE A (ADSL OVER POTS) AND ANNEXE B (ADSL OVER ISDN) AND ITU 922.2 (G.LITE) AND ANSI T1.413.
s DIRECT INTERFACE TO PCI BUS (PCI
RELEASE 2.2 AND COMPLIANT WITH MICROSOFT PC99 & PC2001 SPECIFICATION)
s DIRECT
INTERFACE TO USB RELEASE 1.1 SPECIFICATION)
(USB
s DIRECT INTERFACE TO THE EXTERNAL
SERIAL MEMORY TO SUPPORT PCI/USB USER'S CONFIGURATION
s DIRECT ANALOG FRONT END INTERFACE
FOR ST70136 OR ST70134
s 4 TO 8 GPIO DEPENDING ON SELECTED
AFE AND EXTERNAL MEMORY CONFIGURATION USED
s CLOCK & RESET INTERFACE s 1.8V AND 3.3V POWER SUPPLY s TTL
LOGIC LEVELS (DEPENDING ON PADS) COMPATIBLE
s POWER MANAGEMENT s LOW POWER CONSUMPTION : 0.4W s TQFP 144
ST70137 SOFTWARE FEATURES
s RFC 2364 PPP OVER ATM s UNI 3.0, 3.1, 4.0 SIGNALING s UBR, CBR s AAL0, AAL5 s NDIS5.0 PCI DRIVER AND USB DRIVER
September 2001
TQFP144 ORDER CODE: ST70137TQFP
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ST70137
TYPICAL APPLICATION
PCI or USB ST70137 POTS Line ST70136 or ST70134 ST70137 DMT ST70136 AFE or ST70134 LINE I/F POTS Line
PC
ADSL MODEM
USB
Dongle Modem
or
PCI Board
BLOCK DIAGRAM
USB IF PCI_IF MEM IF
USB_BRIDGE
Bridge
PCI_BRIDGE
CFG_MEMs
CFG_SEL
USB_PCIN_sel
CLK SWITCHER TGB RST
ATM FIFOs
OBC FIFOs
REGs
PERIPHERAL
GPIO IF
Utop FSM ADSL uP
OBC_IF TAP AFE IF
TOSCA v. 2.0
OBC: On Board Controller TGB: Time Generation Block TAP: Test Access Protocol Utop FSM: Utopia Finite State Machine
2/22
ST70137
SOFTWARE ARCHITECTURE
User Applications: Netscape, NetMeeting, etc. Trace Tools Ring 3: User Mode
NDIS 5 Control Win32 kernel Modem SW Data
Hw Abstraction Layer
USB Driver
PCI Driver
Registry
USBD SYS - MS Bus Driver
UHCD.SYS
OHCD.SYS
Ring 0: Kernel Level Hardware
UHCI (Intel)
OHCI (NEC and Others)
USB Device
PCI Device
3/22
ST70137
PIN CONNECTIONS
CTRLDIN GPIO[4] / AFEWR GPIO[5] / COMP_ROUT D_VDD_PLL A_VDD_PLL D_VSS_PLL A_VSS_PLL CTRLDOUT
AFERXD[3]
AFERXD[2]
AFERXD[1]
AFERXD[0]
AFETXD[3]
AFETXD[2]
AFETXD[1]
AFETXD[0]
AFERST
VDD1.8
VDD3.3
VDD1.8
TRSTB
CLWD
MCLK
TDO
TMS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125124 123 122 121120 119 118 117116 115 114 113 112 111 110 109 VDD 3.3 GPIO[0] GPIO[1] GPIO[2] GPIO[3] VSS DMINUS DPLUS VSS RSTN CFG_SCE CFG_SCK/ GPIO[6] CFG_SDI CFG_SDO/GPIO[7] VDD 1.8 C_EXT VSS VDD 3.3 VR50F PCI_INTAN PCI_RSTN VSS PCI_CLK PCI_GNTN VDD 3.3 PCI_REQN PCI_PMEN VSS PCI_AD[31] PCI_AD[30] VDD 3.3 PCI[AD29] PCI_AD[28] VSS PCI_AD[27] PCI_AD[26] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PCI_DEVSELN PCI_FRAMEN PCI_CBE3N PCI_CBE2N PCI_STOPN PCI_TRDYN PCI_CBE1N PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_IRDYN PCI_AD[15] PCI_IDSEL PCI_PAR PERRN SERRN VSS VSS VSS VSS VSS VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD1.8 VDD3.3 VDD3.3 VSS 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 VDD3.3 ACTD PWDN SUSPENDN SUSPEND LD_PWDN VSS AFESEL USB_PCIN_SEL CFG_MEM_SEL VAUX_D_USB_SP VDD1.8 VR50 PCI_AD[0] PCI_AD[1] PCI_AD[2] VDD3.3 PCI_AD[3] PCI_AD[4] VSS PCI_AD[5] PCI_AD[6] VDD3.3 PCI_AD[7] PCI_CBE0N VSS PCI_AD[8] PCI_AD[9] VDD3.3 PCI_AD[10] PCI_AD[11] VSS PCI_AD[12] PCI_AD[13] VDD3.3 PCI_AD[14]
VSS 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TCK
TDI
ST70137
4/22
ST70137
PIN LIST
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Note
NAME VDD3.3 GPIO[0] GPIO[1] GPIO[2] GPIO[3] VSS DATA_MINUS DATA_PLUS VSS RSTN CFG_SCE CFG_SCK/GPO[ 6] CFG_SDI CFG_SDO/GPO[ 7] VDD 1.8 C_EXT VSS VDD3.3 VR50F PCI_INTAN PCI_RSTN VSS PCI_CLK PCI_GNTN VDD3.3 PCI_REQN PCI_PMEN VSS PCI_AD[31] PCI_AD[30] VDD3.3 PCI_AD[29] PCI_AD[28] VSS
TYPE P I/O I/O I/O I/O P I/O I/O P I O O I O P P
DRIVE
DESCRIPTION Power supply pins 3.3V for I/O pads (not PCI)
4mA 4mA 4mA 4mA Ground
Ground
4mA 4mA
4mA Power supply pins 1.8V for Core External Capacitor to reduce ripple of the internal DC regulator 1 Ground
P P OD I P I I P O OD P I/O I/O P I/O I/O P 8mA 8mA 8mA 8mA 8mA 8mA 8mA
Power supply pins 3.3V for PCI I/O pads ESD protection Power Supply for DC regulator (3.3V) Low, High Impendance
Ground
Power supply pins 3.3V for PCI I/O pads ESD protection
Ground
Power supply pins 3.3V for PCI I/O pads
Ground
1. Pin C_EXT must be connected:
10nF
1F
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ST70137
PIN LIST (continued)
PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 NAME PCI_AD[27] PCI_AD[26] VDD3.3 PCI_AD[25] PCI_AD[24] VSS PCI_CBE_N[3] PCI_IDSEL VDD3.3 PCI_AD[23] PCI_AD[22] VSS PCI_AD[21] PCI_AD[20] VDD3.3 PCI_AD[19] PCI_AD[18] VSS PCI_AD[17] PCI_AD[16] VDD3.3 VDD1.8 PCI_CBE_N[2] PCI_FRAMEN VSS PCI_IRDYN PCI_TRDYN VDD3.3 PCI_DEVSELN PCI_STOPN VSS PCI_PERRN PCI_SERRN VDD3.3 PCI_PAR PCI_CBE_N[1] VSS PCI_AD[15] PCI_AD[14] TYPE I/O I/O P I/O I/O P I/O I P I/O I/O P I/O I/O P I/O I/O P I/O I/O P P I/O I/O P I/O I/O P I/O I/O P I/O I/O P I/O I/O P I/O I/O 8mA 8mA 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads Power supply pins 1.8V for Core 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA Ground Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA 8mA Ground DRIVE 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection DESCRIPTION
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ST70137
PIN LIST (continued)
PIN 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 NAME VDD3.3 PCI_AD[13] PCI_AD[12] VSS PCI_AD[11] PCI_AD[10] VDD3.3 PCI_AD[9] PCI_AD[8] VSS PCI_CBE_N[0] PCI_AD[7] VDD3.3 PCI_AD[6] PCI_AD[5] VSS PCI_AD[4] PCI_AD[3] VDD3.3 PCI_AD[2] PCI_AD[1] PCI_AD[0] VR50 VDD1.8 VAUX_D/USB_SP CFG_MEM_SEL USB_PCIN_sel AFESEL VSS LPDWDN SUSPEND SUSPENDN PWDN ACTD VDD3.3 TEST TEST TEST AFERST TYPE P I/O I/O P I/O I/O P I/O I/O P I/O I/O P I/O I/O P I/O I/O P I/O I/O I/O P P I I I I P O O O O I P I/O I/O I/O O 4mA Power supply pins 3.3V for I/O pads (not PCI) Test Reserved - Must be fixed to ground Test Reserved - Must be fixed to ground Test Reserved - Must be fixed to ground 4mA 4mA 4mA 4mA Ground 8mA 8mA 8mA 3.3V Power supply for DC regulator Power 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads 8mA 8mA Ground 8mA 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 8mA 8mA Ground DRIVE DESCRIPTION Power supply pins 3.3V for PCI I/O pads ESD Protection
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ST70137
PIN LIST (continued)
PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Note 1.
COMP_CELL 100K 1%
NAME VSS AFETXD[0] AFETXD[1] AFETXD[2] AFETXD[3] VSS AFERXD[0] AFERXD[1] AFERXD[2] AFERXD[3] VDD1.8 COMP_CELL VSS MCLK VDD3.3 CLWD AFEWR/GPIO[5] CTRLDOUT CTRLDIN/GPIO[4] VSS TEST VDD1.8 TDI TDO TMS TCK TRSTB VSS VDD_APLL VSS_APLL VDD_DPLL VSS_DPLL
TYPE P O O O O P I I I I P O P I P I I/O O I/O P I/O P I O I I I P P P P P
DRIVE Ground 8mA 8mA 8mA 8mA Ground
DESCRIPTION
Power supply pins 1.8V for Core Compensation cell resistor 1 Ground
Power supply pins 3.3V for I/O pads (not PCI)
4mA 4mA 4mA Ground Test Reserved - Must be fixed to ground Power supply pins 1.8V for Core
4mA
Ground PLL Analog power supply 1.8V PLL Analog Ground PLL digital power supply 1.8V PLL digital Ground
Note:
PCI section from pin 16 to pin 96 (included): all the power supply pins (at 3.3V) included in this section are intented for PCI I/O pads.
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ST70137
PIN DESCRIPTION
Signal Name PCI INTERFACE PCI_CLK I PCI Clock. (33 MHz) The rising edge of this signal is the reference upon which all the other PCI signals are based except for PCI_RSTN and PCI_INTAN. The maximum PCI_CLK frequency for ST70137 is 33MHz and the minimum is DC. PCI_RSTN I I L PCI Reset Reset bring ST70137 in a known state: - All PCI bus output signal tri-stated - All open drain signals floated - All registers set to their factory defaults - All FIFOs emptied - GPIO signals tri-stated - Sachem Macrocell initialized - Clock of Adsl_Up stopped - AFE set in Power down mode PCI_REQN O H L PCI Request This signal is sourced by an agent wishing to become a bus master. It is a point to point signal and each master has its own PCI_REQN. PCI_GNTN I I L PCI Grant The PCI_GNTN signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted. PCI_AD[31:0] I/O I PCI Multiplexed Address/Data Bus Address and data are multiplexed on the same PCI bus pins. A PCI bus transaction consists of an address phase followed by the one or more data phase. An address phase occurs on the PCLK cycle in which PCI_FRAMEN is asserted. A data phase occurs on PCLK cycles in which PCI_IRDYN and PCI_TRDYN are both asserted. Direction Init Status Polarity Signal Description
9/22
ST70137
PIN DESCRIPTION (continued)
Signal Name PCI_CBE_N[3:0] Direction I/O Init Status I Polarity L Signal Description PCI Multiplexed Bus Command Mode Bus command and byte enables are multiplexed on the same pins. These pins define the current bus command during an address phase. During a data phase, these pins are used as Byte Enables, with PCI_CBE_N[0] (LSB) enabling byte 0 and PCI_CBE_N[3] enabling byte 3 (MSB). C/BE[3:0]=Command Type 0000 = Interrupt Acknowledge 0001 = Special Cycle 0010 = I/O Read 0011 = I/O Write 0100 = Reserved 0101 = Reserved 0110 = Memory Read 0111 = Memory Write 1000 = Reserved 1001 = Reserved 1010 = Configuration Read 1011 = Configuration Write 1100 = Memory Read Multiple 1101 = Memory Write Multiple 1110 = Memory Read line 1111 = Memory Write and Invalidate PCI_PAR I/O I H PCI Parity (even) Parity is always driven as even from all PCI_AD[31:0] and PCI_CBE[3:0] signals. The parity is valid during the clock following the address phase and is driven by the bus master. During a data phase for write transactions, the bus master sources this signal on the clock following PCI_IRDYN active; during data phase for read transactions, this signal is driven by the target and is valid on the clock following PCI_TRDYN active. The PCI_PAR signal has the same timing as PCI_AD[], delayed by one clock. PCI Cycle Frame This signal is driven by current bus master to indicate the beginning and duration of a bus transaction. When PCI_FRAMEN is first asserted, it indicates a bus transaction is beginning with a valid addresses and bus command present on PCI_AD[31:0] and PCI_CBE[3:0]. Data transfer continue until PCI_FRAMEN is asserted. PCI_FRAMEN de-assertion indicates the transaction is in final data phase or has completed. PCI Device Select This signal is driven by a target decoding and recognizing its bus address. This signal informs a bus master whether an agent has decoded a current bus cycle. PCI Initiator Ready This signal is always driven by the bus master to indicate its ability to complete the current data phase. During write transactions it indicates PCI_AD[] contains valid data. PCI Initializatio n Device Select This pin is used as chip select during configuration read or write transactions.
PCI_FRAMEN
I/O
I
L
PCI_DEVSELN
I/O
I
L
PCI_IRDYN
I/O
I
L
PCI_IDSEL
I
I
H
10/22
ST70137
PIN DESCRIPTION (continued)
Signal Name PCI_TRDYN Direction I/O Init Status I Polarity L Signal Description PCI Target Ready This signal is driven by the select target to indicate the target is able to complete the current data phase. During read transactions, it indicates PCI_AD[] contains valid data. Wait states occur until both PCI_TRDYN and PCI_IRDYN are asserted togheter. PCI Parity Error Only for reporting data parity errors for all bus transactions except for special cycles. It is driven by the agent receiving data two clock cycles after the parity was detected as an error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. PCI System Error Used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. PCI Interrupt A This signal is defined as optional and level sensitive. Driving it low will interrupt to the host. The PCI_INTAN interrupt is to be used for any single function device requiring an interrupt capability. PCI Power Management Event This signal is used to indicate that a power management event has been detected. The PCI_PMEN signal is asynchronous with respect to the PCI clock; it is set (if enabled) by the low to high transition of the ACTD signal. PCI Stop This signal indicates the current target is requesting the master to stop the current transaction.
PCI_PERRN
I/O
I
L
PCI_SERRN
O
Z
L
PCI_INTAN
O
Z
L
PCI_PMEN
O
Z
L
PCI_STOPN
I/O
I
L
USB INTERFACE
DPLUS DMINUS I/O I/O I I + Differential positive USB data input/output. Differential negative USB data input/output.
MISCELLANEOUS INTERFACE GPIO[3:0] I/O I General Purpose I/O Bus These signals are controlled by internal registers located inside ADSL uP block. At the Power-up, Hardware or Software Reset the input direction is chosen. Select Internal [1] or External [0] PCI/USB configuration memory. Select PCI [0] or USB [1] Interface Selecting USB interface and if all Test Pins are set to default value, all the PCI Pads are deactivated. The power supply for this section can be not provided. The PCI section is frozen. Selecting PCI interface the DMINUS and DPLUS has to be set to the low level (reset mode). The PLL is in power down and no any clock will be provided to the USB section. VAUX Detect when USB_PCIN_sel = [0] or USB SELF POWERED when USB_PCIN_sel = [1].
CFG_MEM_SEL USB_PCIN_sel
I I
I I
-
VAUX_D / USB_SP
I
I
-
11/22
ST70137
PIN DESCRIPTION (continued)
Signal Name Direction Init Status Polarity Signal Description
CLOCK & RESET INTERFACE MCLK RSTN AFE INTERFACE AFETXD[3:0] O L AFE Transmit Data Nibble Bus The signal changes are synchronized to the rising edge of MCLK clock signal. AFE Receive Data Nibble Bus The signal changes are synchronized to the rising edge of MCLK clock signal. Start of word indication This signal is the word clock used to enable shift of data. It occurs on CTRLDOUT signal to indicate the first data of the nibble sequence. The CLWD frequency is equal to MCLK/4. Transmit Control Word Data to AFE The data is shifted out from internal register on the rising edge of MCLK during CLWD assertion. Select ST-70136 [0] or ADSL_C [1]. AFE Reset This signal is connected to the internal PCFW (USB_PCIN_SEL = [0]) or UCFW registers (USB_PCIN_SEL = [1]) if AFESEL = [0], or to the Sachem GPOUT register if AFESEL = [1]. Not usable in USB mode. AFE Write control output signal (AFESEL = 0), or General Purpose I/O pin. The selection is performed writing the proper bit in the PCFW or UCFW (depending on status of USB_PCIN_SEL pin) registers. At the power-on or hardware reset the GPIO[5] function is selected. Receive Control word data from AFE (AFESEL = 0), or General Purpose I/O pin. The selection is performed writing the proper bit in the PCFW or UCFW (depending on status of USB_PCIN_SEL pin) registers. At the power-on or hardware reset the GPIO[4] function is selected ACTD I I H Activation Tone Detect [1] (or Wake Up signal). When PCI IF has been selected, the Low to High transition of ACTD asserts the PCI_PMEN signal (if this last has been enabled) and generates an interrupt event. When USB IF has been selected, the Low to High transition of ACTD de-asserts the SUSPEND signal and re-enable the internal ST70137 activity. Suspend Mode Indication. Suspend Mode Indication Negated. AFE Power Down. Line Driver Power Down [1]. I I I I L 35.328 MHz Master Input Clock. Asynchronous Master USB_PCI_SEL = `1'). Input Reset (active if
AFERXD[3:0]
I
I
-
CLWD
I
I
H
CTRLDOUT
O
H
L
AFESEL AFERST
I O
I L
L
AFEWR / GPIO[ 5]
I/O
I
L/-
CTRLDIN / GPIO[4]
I
I
L/-
SUSPEND SUSPENDN PWDN LDPWDN
O O O O
L H H H
H L H H
12/22
ST70137
PIN DESCRIPTION (continued)
Signal Name Direction Init Status Polarity Signal Description
CFG_MEM INTERFACE CFG_SCE O L H Chip Enable This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. This pin has to be connected directly to the EEPROM's chip select pin. Serial Clock or General Purpose Output Pin 6 depending on the internal selection. The selection is performed writing the proper bit inside the PCFW or UCFW register. At the power-on or hardware reset the CFG_CLK functionality is selected. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. Serial Data Input Data going into this pin has to be generated on the rising edge of CFG_SCK. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. Serial Data/Address Output General Purpose Output Pin 7 depending on the internal selection. The selection is performed writing the proper bit inside the PCFW or UCFW register. At the power-up or hardware reset the CFG_SDO functionality is selected. The CFG_SDO data change is synchronous with the falling edge of CFG_SCK. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol.
CFG_SCK/GPO[ 6]
O
L
-
CFG_SDI
I
I
H
CFG_SDO/GPO[ 7]
O
L
-
JTAG INTERFACE TDI TDO TMS TCK TRSTB I O I I I IH IH IL IL L L JTAG Test Data Input. JTAG Test Data Output. JTAG Test Mode Select. JTAG Test Clock. JTAG Reset (active Low).
TEST CONDITION All Ouputs have been loaded with.
Outputs PCI USB * Others
* See text scheme at page 20.
Minimum 0 0 0
Maximum 50 50 15
Unit pF pF pF
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ST70137
TIMING SPECIFICATION
MCLK Master Clock Symbol F T Th Parameter Clock frequency Clock Period Clock Duty cycle 40 Minimum Typical 35.328 28.3 60 Maximum Unit MHz ns %
AFE IF Transmit & Receive Signals
MCLK T AFERXD Ts1 Th1
AFETXD Tv1 CLWD Ts2 Th2
Tv2 CTRLDOUT
AFEWR Ts3 CTRLDIN
Tv3
Th3
AFE IF Transmit & Receive signals Ts1 Th1 Tv1 Data Setup Time Data Hold Time Data Valid Time Data Setup Time Data Hold Time Data Valid Time Data Setup Time Data Hold Time Data Valid Time 20 1 18 5 6 18 5 7 13 ns ns ns ns ns ns ns ns ns
Ts2 Th2 Tv2 Ts3 Th3
Tv3
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ST70137
CFG_MEM IF Signals with PCI = 30.3ns
CFG_SCK
Tsclk CFG_SDO Tv1
Th CFG_SDI
Ts CFG_SCE Tv2
CFG_MEM IF signals with PCI = 30.3ns * Symbol Ts Th Tv1 Tv2 Tsck Parameter Data Setup Time Data Hold Time Data Valid Time Data Valid Time SCK Clock period: - USB 48MHz - PCI 33MHz
* PCI conditions are more restrictive than USB conditions.
Minimum 45 0
Typical
Maximum
Unit ns ns
970 160 USB_CLK / 64 PCI_CLK / 64
ns ns ns
GPIO IF
PCI_CLK Tv GPIO OUTPUT
GPIO IF Symbol Tv Parameter Output Data Valid from PCI_CLK Minimum Typical Maximum 22 Unit ns
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ST70137
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter VDD 3.3 VDD 1.8 Ptot Tamb Tstg VESD Description Supply Voltage Supply Voltage Total Power Dissipation Ambient Temperature 1.5ml airflow Storage Temperature ESD Protection (HBM) 0 Minimum 3.0 1.62 Typical 3.3 1.8 Maximum 3.6 1.98 450 70 +150 Units V V mW C
-65 2000
C
V
PCI Interface DC Specifications
Parameter Vilp Vihp lip Volp Vohp Cinp Cclkp Cidsel Lpinp Description Input LOW Voltage Input HIGH Voltage Input Leakage Current Output LOW Voltage Output HIGHT Voltage Input Pin Capacitance * CLK Pin Capacitance * IDSEL Pin Capacitance * Pin Inductance * N/A 5 0* Guaranted by design.
USB Interface DC Specifications Nominal DC Characteristics (DPLUS, DMINUS)
Parameter VDI VCM V SE VOH V OL ILO CIN RD Description Differential Input Sensitivity [(D+) - (D-)] Differential Common Mode Range Single Ended Receiver Threshold High Level Output Static Voltage (RL of 15K to GND Low Level Output Static Voltage (RL of 1.5K to 3.6V) Minimum 0.2 0.8 0.8 2.8 2.5 2 3.6 0.3 Typical Maximum Units V V V V V A pF
Hi-Z State Data Line Leakage Current (0V < Vin < 3.3V)
Transceiver Capacitance (Pin to GND) * Driver Output Resistance (steady state drive) 28
30
10 44
* Guaranted by design.
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ST70137
Other Signals DC Characteristics The values presented in the following table apply for all inputs and/or outputs unless otherwise specified. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device.
Symbol IIN I OZ I PU I PD Parameter Input Leakage Current Tristate Leakage Current Pull Up Current Pull Down Current Test Condition Minimum -4 -4 -15 +15 -40 +30 Typical Maximum +4 +4 -125 +125 Units A A A A
Vin = VSS, VDD no pull up/pull down Vin = VSS, VDD no pull up/pull down
Vin = VSS Vin = VDD
Suspend Mode Current Consumption
Symbol I518 I533 Parameter Suspend Mode Current Consumption on 1.8V Suspend Mode Current Consumption on 3.3V Test Condition Minimum Typical 350 150 Maximum Units A A
Temperature = 25C Temperature = 25C
AC Specifications PCI Signaling AC Specifications
Symbol Ioh Parameter Switching Current High Test Condition 0 < Vout 0.3VDD Vout = 0.7VDD Iol Switching Current Low VDD > Vout 0.6VDD Vout = 0.18VDD Icl Ich Tr Tf Low Clamp Current * High Clamp Current * -3 < Vin -1V -25 + (Vin + 1) / 0.015 16V DD 38VDD Minimum -12V DD -32VDD Typical Maximum Units mA mA mA mA mA mA 4 4 V/ns V/ns
VDD + 4 > Vin VDD + 1 25 + (Vin - VDD - 1) / 0.015 1 1
Unloaded Output Rise Time * 0.2VDD to 0.6VDD Unloaded Output Fall Time * 0.6VDD to 0.2VDD
* Guaranted by design.
Timing Specifications PCI Clock Specifications
Symbol Tc Th TI Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Slew Rate *
* Guaranted by design.
Test Condition
Minimum 30 11 11 1
Typical
Maximum 50
Units ns ns ns
4
V/ns
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ST70137
PCI Clock Waveform 5V
2.4V 2.0V 1.5V 0.8V 0.4V Th Tc TI
PCI Clock Waveform 3.3V
0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD Th Tc TI
PCI Timings
Symbol Tval Tval(ptp) Ton Toff Tsu Tsu(ptp) Th Trst Trst-clk Trst-off Parameter Clock to Signal Valid Delay (bused signals) Clock to Signal Valid Delay (point to point) Float to Active Delay Active to Float Delay Input Set up Time to Clock (bused signals) Input Set up Time to Clock (point to point) * Input Hold Time from Clock Reset Active Time after Power Stable Reset Active Time after CLK Stable ** Reset Active to Output Float Delay ** 7 10, 12 * 0 1 100 40 Minimum 2 2 2 28 Typical Maximum 11 12 Units ns ns ns ns ns ns ns ms s ns
* PCI REQN and GNTN are point-to-point signals and have different output valid delay and input setupt times than do bused signals. REQN has set up of 12ns and GNTN of 10ns. All other signals are bused. ** Guaranted by design.
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ST70137
CLK
Tsu
Th
Input
Tval
Output
Tri-state Output
Ton Toff
USB Interface AC Specifications (1.1 version) AC Characteristics (D+, D-)
Symbol tDR tR tF VCRS Parameter Average bit rate (12 M/s 0.05%) Rise Time between 10% and 90% (see Figure Rise and Fall Time Measures) Fall Time 10% and 90% (see Figure Rise and Fall Time Measures) Output Signal Crossover Voltage Test Conditio n Minimum 11.97 4 4 1.3 Typical Maximum 12.03 20 20 2 Units Mbps ns ns V
USB Test Scheme
Test
2
Test
1
50pF 50pF
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ST70137
Rise and Fall Time Measures
TR 90% 90% TF
10%
10%
Input / Output TTL Generic Characteristics The value presented in the following table apply for all TTL inputs and/or outputs unless otherwise specified.
Symbol V IL VIH VILHY VIHHY VHY VOL VOH Parameter Test Condition Minimum Typical Maximum 0.8 2.0 Slow edge < 1V/s Slow edge < 1V/s Slow edge < 1Vs IOUT = XmA (see Note) IOUT = XmA (see Note) 2.4 0.9 1.3 0.4 1.35 1.9 0.7 0.4 Units V V V V V V V
Low Level Input Voltage
High Level Input Voltage Low Level Threshold, falling * Low Level Threshold, rising * Schmitt Trigger Hysteresis * Low Level Output Voltage High Level Output Voltage
* Guaranted by design.
Note:
The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA.
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ST70137
PACKAGE MECHANICAL DATA (TQFP144 - 20 x 20 x 1.40 mm)
A A2 144 e A1 109 0,076 mm 0.03 inch 108
SEATING PLANE
1
36
73
c
37
D3 D1 D
72
L1
L
E3 E1 E
0,25 mm .010 inch
GAGE PLANE
K
Millimeters Dimension Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 1.00 0 (Min.), 7 (Max.) 0.75 0.018 1.40 0.22 Typical Maximum 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.0067 0.0035 Minimum
Inches Typical Maximum 0.063 0.006 0.055 0.0087 0.057 0.011 0.008 0.866 0.787 0.689 0.020 0.866 0.787 0.689 0.024 0.039 0.030
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B
ST70137
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http ://www.st.com
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